1. Field of the Invention
The present invention relates to an improvement of a circuit structure for repairing a defective bit in a semiconductor memory device.
2. Description of the Background Art
Generally, in a semiconductor memory device, spare rows and spare columns are provided in a memory cell array in order to repair defective bits so as to improve production yield.
FIG. 1 schematically shows a whole structure of a conventional semiconductor memory device having a redundant bit structure.
Referring to FIG. 1, the conventional semiconductor memory device comprises a memory cell array 1 having a plurality of memory cells MC arranged in n rows and n columns. N rows (word lines) R1 to Rn each having connected thereto a row of memory cells, and n columns (bit line pairs) C1 to Cn each having connected thereto a column of memory cells are arranged in the memory cell array 1. A spare row SR and a spare column SC are provided to repair a defective bit (memory cell) at prescribed positions (in FIG. 1, at the first row and (n+1)-th column) of the memory cell array 1.
The rows R1 to Rn are respectively connected to output signal lines X1 to Xn of a row decoder 3. The row decoder 3 decodes externally applied X address signals (row address signals) A0 to Ak to activate one of the output signal lines X1 to Xn.
The columns C1 to Cn are respectively connected to output signal lines Y1 to Yn of a column decoder 6. The column decoder 6 decodes externally applied Y address signals (column address signals) B0 to Bm to select one of the output signal lines Y1 to Yn to activate the selected output signal line. The output signals Y1 to Yn of the column decoder 6 are applied to gates of column selection gates 90a, 90b in order to selectively connect the columns C1 to Cn to a common data line (not shown) in response to an output signal from the column decoder 6.
The column selection gate 90a connects a bit line BLj of a column Cj (j=1 to n) to the common data line, and the column selection gate 90b connects a complementary bit line BLj of the column Cj to a complementary common data line. The group of gates formed of the column selection gates 90a and 90b constitute a column selection gate 9. The output signals from the column decoder 6 are transmitted to the column selection gate 9 through fuses (fusible element) f1 to fn. The fuses f1 to fn can be melt by, for example, a laser beam. A high resistance r is provided in parallel to each of the fuses f1 to fn in order to maintain, when the fuse is melt, the gate potential of the column gates 90a and 90b connected to the melt fuse at the ground potential level.
In order to repair a row including a defective bit (memory cell), a programming circuit 30, a spare row decoder 31 and a spare row driver SXD are provided. An example of this structure is disclosed in, for example, 1982 IEEE ISSCC Digest of Technical Papers, February,. 1982, pp. 252 to 253 by Smith et al. The programming circuit 30 stores the address of the row including a defective bit. Generally, the programming circuit 30 has the same structure as a unit row decode circuit constituting the row decoder 3, and in most cases, a fuse included therein is melt by a laser beam so as to store the address of the row including the defective bit. The spare row decoder 31 outputs a spare row selecting signal as well as a signal NED to render the row decoder 3 inactive in response to an activating signal from the programing circuit 30. The row driver SXD drives the spare row SR in response to the spare row selecting signal from the spare row decoder 31 to set the spare row SR at a selected state.
A programming circuit 61 and a spare column decoder 60 are provided for selecting a spare column (redundant column) SC. The programming circuit 61 stores the address of the column including a defective bit and, when an external Y address signals B0 to Bm designate the column including the defective bit, outputs an activating signal. The spare column decoder 60 outputs a signal for selecting the spare column SC in response to the activating signal from the programming circuit 61. The operation will be described in the following.
First, the operation where there is no defective memory cell will be described. The row decoder 3 decodes the externally applied X address signals A0 to Ak and outputs a signal for selecting one of the rows R1 to Rn to one of the output signal lines X1 to Xn. Consequently, the potential of the row Ri (the selected row is represented as Ri) rises, so that the row Ri is set at the selected state. Accordingly, the information in the memory cells MC connected to the selected row Ri is read to each of the columns C1 to Cn. Then, signal potential of one of the output signal lines Y1 to Yn rises in response to the decoded Y address signal from the column decoder 6. Now, the selected column is represented as Ci. On this occasion, the potential of the output signal line Yi of the column decoder 6 rises, the column selection gates 90a and 90b are set at the on state, and the column Ci is connected to the common data line. Thereafter, reading or writing of data from or to the memory cell positioned at the intersection of the selected row Ri and the selected column Ci is carried out.
Now, let us assume that a defective memory cell exists in the memory cells connected to the row Ri. The presence/absence of the defective memory cell is found through a function test of the semiconductor memory device. First, the address of the row Ri having a defect is written in the programming circuit 30 for repairing the row. The writing of the address into the programming circuit 30 is generally carried out by cutting a fuse by a laser, as described above. When externally applied X address signals A0 to Ak designate the row Ri, then the programming circuit 30 is activated and the spare row decoder 31 operates. The spare row decoder 31 in operation sets the spare row SR at the selected state through the spare row driver SXD and activates the signal NED, so as to inactivate the row decoder 3. Consequently, the row Ri including the defective memory cell is replaced by the spare row SR, whereby the row Ri is repaired.
Now, let us assume that a defective memory cell exists in a column Ci. In that case, the address of the column Ci including the defective memory cell is written by cutting a fuse, for example, to the programming circuit 61 for repairing the column, as in the case of repairing the row. At that time, the fuse fi connected to the output signal line Yi for selecting the column Ci including the defective memory cell is also cut, so that defective column Ci is cut away from the column decoder 6. Consequently, the column Ci including the defective memory cell is kept at the non-selected state. When the externally applied Y address designates the column Ci, the spare column decoder 60 operates through the programming circuit 61, whereby the spare column SC is selected. Therefore, the column Ci including the defective memory cell is replaced by the spare column SC, and the defective column Ci is repaired.
The defective bit repairing circuit in the conventional semiconductor memory device is structured as described above in which the programming circuits, the spare row decoder, the spare column decoder and the like are necessary, increasing the area of the chip.
The programming of the address in the programming circuit is generally carried out by cutting of a fuse. However, as shown as an example in the aforementioned article, there are a large number of fuses included in the programming circuit, and a number of fuses must be cut for programming a defective row or column. Since the programming of a defective row or column is carried out chip by chip in this system, the throughput may be reduced and errors in cutting the fuses may be generated during the repairing process, which leads to lower success rate in repair, and accordingly to reduced production yield of the semiconductor memory device.
When a defective row is selected and to be repaired, the row decoder is made inactive by a signal NED from a spare row decoder. Namely, the row decoder is once activated and thereafter inactivated in response to the signal NED, which means that the row including the defective memory cell (bit) is also selected once. In order to prevent influences effected by the state of selection of the row including the defective bit, it is necessary to connect a selected memory cell to the common data line after the signal potential of the selected row becomes stable, which increases the time of access.
A redundancy scheme for repairing a defective cell in a memory device is disclosed in S. S. Eaton, Jr's U.S. Pat. No. 4,389,715, "An Ultralow Power 8K.times.8-Bit Full CMOS RAM with a Six-Transistor Cell", by K. Ochii et al. IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, October 1982, pp 798 to 803, and in Japanese Patent Publication No. 61-35636.
U.S. Pat. No. 4,389,715 discloses a memory device including a circuit for storing row or column address of a defective memory cell provided for an address buffer, a circuit for comparing the output from the address buffer and the stored address in the storing circuit, and a circuit for selecting spare cells in response to the output from the comparing circuit.
The article of Ochii et al discloses a redundancy circuit of 1 row and 2 columns for repairing defective cells. The redundancy circuit has a program circuit in which an address of a defective row or column is programmed by cutting of a fuse by means of laser. The program circuit is provided with a spare enable latch for preventing DC current.
Japanese Patent Publication (Kokoku) No. 61-35636 discloses a memory device having a switch circuit provided between a row or a column and a decoder output. The switching circuit has a fuse, and selection/non-selection of a corresponding row or column is determined by cutting this fuse.